In the field of semiconductor research, three-dimensional integrated circuits (3D ICs) have emerged as a promising solution to the constant demand for more power in a smaller package.
But what are 3D ICs, exactly, and where is this technology headed?
In general, electronic signals are transmitted faster as the density of transistors increases within a given space. For years, this meant squeezing smaller transistors into more compact footprints, but this tactic is reaching its physical limitations.
Theoretically, manufacturing larger chips would help, but this isn’t a viable option for two reasons. Firstly, it’s geometrically easier to fit more, smaller chips onto a silicon wafer than a handful of larger chips. Secondly, all it takes is a particle of dust to contaminate a clean room and ruin the manufacturing process; producing small batches of large chips is effectively gambling on putting all your silicon eggs in one wafer-shaped basket. Instead, manufacturing smaller chiplets allows for little mistakes that don’t impact the entire wafer.
The object of the game then becomes to discover how to connect multiple chiplets as efficiently as possible to reap the same performance benefits of one big chip in a petite, budget-friendly package. Enter, die stacking technologies.
The evolution of die stacking
Die stacking has been around since the earliest multi-chip modules (MCMs) of the 1970s, but there hasn’t been a need for engineers to advance this tech and make it scalable until the recent AI boom. These developments have largely been centered around the introduction of the interposer: a layer of (typically) silicon embedded with insulated copper pathways called Through-Silicon Vias (TSVs) that connect the ICs on systems in packages (SiPs).
When SiPs are “stacked” side-by-side, they’re referred to as 2.5D; when they’re stacked vertically, they’re referred to as 3D — however, as Dick James, Senior Technology Analyst at Siliconics, puts it, these devices are “3D, but not 3D.” That title is reserved for monolithic 3D integrated circuits.
“Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs present “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale,” reported a study led by Perrine Batude of the CEA-Leti research institute in France.
Francoise von Trapp, the “Queen of 3D” at 3DInCites tasked herself with the duty of explaining the difference between the two categories of 3D integrated circuits on a deeper level.
“3D TSVs involve taking two finished device wafers (either from the same or different fabs) and vertically interconnecting them at the chip level with Through-Silicon Vias,” she explains. “On the other hand, with monolithic, you never have [a] second wafer, but rather a 100nm layer of crystallized silicon, which results in a multiple order of magnitude of difference in both the size of the vias and the final device size….The end device will be smaller and thinner, [and the] interconnection is 10,000 times higher due to the number of vertical connections.”
Design challenges to true 3D integrated circuits
While monolithic ICs have major performance advantages over 3D TSVs, all this power in a tiny footprint comes with a price — both literally and in the form of heat.
True monolithic 3D ICs are the metropolises of semiconductors and, like all major cities, they’re expensive and crowded. In the technical world, this translates to high design costs and overheating that greatly impacts efficiency. Researchers are dabbling with high thermal conductivity insulators and configurations of atomically-thin transistors to try to solve the overheating issue, which is why we aren’t seeing true 3D integrated circuits on commercial markets, yet.
Despite this unresolved solution to a complex problem, one thing is certain: vertical stacking ICs have caught the interest of those across the industry. With major players already investing in R&D for 3D stacking technology, we will likely witness a race to see who will come out on top.
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