An army of semiconductor industry titans have joined forces for a tactical transformation of semiconductor chips.
Rene Descartes likely didn’t have quantum computing in mind in 1637 when he wrote the words “Divide each difficulty into as many parts as is feasible and necessary to resolve it.” But with that, he paved the way for an eloquent solution to rising costs and expectations in the semiconductor engineering field: chiplets.
What are chiplets?
Chiplets are what they sound like: small integrated circuits (ICs) that can be combined in a modular way to mix and match different ICs on the same package.
But wait a minute — we just got SoCs (systems on a chip) running at bullet-fast speeds, why are we trying to break everything up again?! It all comes down to cash. Or rather, cache. Or, likely, both.
Cache memory is ultrafast, temporary memory that basically enables the CPU to run modern computers. It’s 10 to 100 times faster than RAM and comes in L1, L2, and L3 forms, where speed decreases with capacitance. L1 is the fastest form of cache memory and the most expensive to produce, but it also boasts the least amount of storage; L2 is slower than L1 but holds more memory.
Cache memory is stored in high-speed static random access memory (SRAM), typically on the CPU itself. The physically closer the SRAM is to the core, the faster the CPU can access the data. But there’s an unavoidable problem with having your entire system on a chip: it gets crowded. Digital circuits (i.e., SRAM and logic circuits) must be placed in optimized locations around analog circuits, which can compromise a substantial portion of the chip and force the SRAM further away from the core.
In 2019, AMD developed the Zen 2: a chip that moved most of the analog circuits from the processor to a separate, less expensive die. Anyone who considers themselves a master at packing a suitcase knows that the configuration of your load directly impacts how much you’re able to pack. That’s why relocating the analog circuits to a separate die doubled the amount of L3 cache between the Zen 1 and Zen 2 releases. L3 improves the performance of L1 and L2 while also doubling the speed of DRAM, increasing the instructions per cycle processor performance metric of the Zen 2 by nearly 30%.
Widescale adoption of CHIPlETS leads to an all-hands-on-deck collaboration
The Zen 2 demonstrated that dedicating separate chiplets for analog and digital circuitry means there’s more room on the digital chip for additional cache, and it’s closer to the processor. It also allows for analog circuits to be mounted on less expensive dies, which makes the entire system less expensive and paves the way for small businesses, startups, or even solo inventors to enter a traditionally cost-prohibitive research and development market.
The Universal Chiplet Interconnect Express (UCIe) is a collaborative effort to standardize an interface that chipmakers can use to combine chiplets from multiple designers on the same package. UCIe was co-developed by AMD, Arm, Advanced Semiconductor Engineering, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and Taiwan Semiconductor, and joined in the board by Nvidia and Alibaba. Shortly after debuting its first CPU integrating a chiplet design, Intel released Pike Creek in September 2023: the first ever UCIe-connected chiplet-based CPU.
Chiplets represent a significant innovation in the field of integrated circuits, offering modular flexibility that can enhance the performance and cost-effectiveness of modern processors. While system-on-a-chip (SoC) designs have been delivering impressive speeds, the demand for cache memory, particularly L3 cache, has led to a new approach. It’s clear that chiplets are not just a technological evolution but also a catalyst for democratizing innovation and expanding the horizons of what’s possible in the world of semiconductor technology.
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